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| MC74HC4066A Advance Information Quad Analog Switch/ Multiplexer/Demultiplexer High-Performance Silicon-Gate CMOS The MC74HC4066A utilizes silicon-gate CMOS technology to achieve fast propagation delays, low ON resistances, and low OFF-channel leakage current. This bilateral switch/ multiplexer/demultiplexer controls analog and digital voltages that may vary across the full power-supply range (from VCC to GND). The HC4066A is identical in pinout to the metal-gate CMOS MC14016 and MC14066. Each device has four independent switches. The device has been designed so that the ON resistances (RON) are much more linear over input voltage than RON of metal-gate CMOS analog switches. The ON/OFF control inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs. For analog switches with voltage-level translators, see the HC4316A. * Fast Switching and Propagation Speeds * High ON/OFF Output Voltage Ratio * Low Crosstalk Between Switches * Diode Protection on All Inputs/Outputs * Wide Power-Supply Voltage Range (VCC - GND) = 2.0 to 12.0 Volts * Analog Input Voltage Range (VCC - GND) = 2.0 to 12.0 Volts * Improved Linearity and Lower ON Resistance over Input Voltage than the MC14016 or MC14066 * Low Noise * Chip Complexity: 44 FETs or 11 Equivalent Gates LOGIC DIAGRAM XA A ON/OFF CONTROL XB B ON/OFF CONTROL XC C ON/OFF CONTROL XD D ON/OFF CONTROL 1 13 4 5 8 6 11 12 ANALOG INPUTS/OUTPUTS = XA, XB, XC, XD PIN 14 = VCC PIN 7 = GND 10 Y D 9Y C ANALOG OUTPUTS/INPUTS 3Y B 2Y A http://onsemi.com MARKING DIAGRAMS 14 PDIP-14 N SUFFIX CASE 646 1 14 SOIC-14 D SUFFIX CASE 751A 1 TSSOP-14 DT SUFFIX CASE 948G 1 14 SOEIAJ-14 F SUFFIX CASE 965 74HC4066A AWLYWW HC4066AD AWLYWW 14 HC40 66A ALYW HC4066AN AWLYYWW 1 A = Assembly Location WL or L = Wafer Lot YY or Y = Year WW or W = Work Week PIN ASSIGNMENT XA YA YB XB B ON/OFF CONTROL C ON/OFF CONTROL GND 1 2 3 4 5 6 7 14 13 12 11 10 9 8 VCC A ON/OFF CONTROL D ON/OFF CONTROL XD YD YC XC ORDERING INFORMATION Device MC74HC4066AN MC74HC4066AD MC74HC4066ADR2 MC74HC4066ADT MC74HC4066ADTR2 MC74HC4066AF Package PDIP-14 SOIC-14 SOIC-14 TSSOP-14 TSSOP-14 SOEIAJ-14 Shipping 2000 / Box 55 / Rail 2500 / Reel 96 / Rail 2500 / Reel See Note 1. FUNCTION TABLE On/Off Control Input L H State of Analog Switch Off On This document contains information on a new product. Specifications and information herein are subject to change without notice. 1. For ordering information on the EIAJ version of the SOIC packages, please contact your local ON Semiconductor representative. Publication Order Number: MC74HC4066A/D (c) Semiconductor Components Industries, LLC, 1999 1 March, 2000 - Rev. 1 MC74HC4066A II II I I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I I I III I I I I I II I I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I I I I II I I I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I I I I I II I I I I I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I III I I I I I II I I I I I I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I IIIIIIIIIII I I II I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIII I I I IIII I I I I IIIIIIIIIIIIIIIIIIIII I IIII II I II IIIIIIIIIIIIIIIIIIIIII II I II IIIIIIIIIIIIIIIIIIIIIII II IIIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIII II I I IIIIIIIIIIIIIIIIIIIIIII II I I IIII I II I I IIIIIIIIIIIIIIIIIIIIIII II I IIII I I I IIIIIIIIIIIIIIIIIIIIIII II I I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIII II I II I IIIIIIIIIIIIIIIIIIIIIII II I I IIIIIIIIIIIIIIIIIIIIIII II I I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIII II I II I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII II I III II I I IIIIIIIIIIIIIIIIIIIIIII II II IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIII II IIIIIIIIIIIIIIIIIIII II II I I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII I IIII III I II I IIIIIIIIIIIIIIIIIIIIIII II III II I IIIIIIIIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIIIIIII MAXIMUM RATINGS* Symbol VCC VIS Vin I Parameter Value Unit V V V Positive DC Supply Voltage (Referenced to GND) Analog Input Voltage (Referenced to GND) Digital Input Voltage (Referenced to GND) DC Current Into or Out of Any Pin Power Dissipation in Still Air, - 0.5 to + 14.0 - 0.5 to VCC + 0.5 - 0.5 to VCC + 0.5 25 750 500 450 mA PD Plastic DIP EIAJ/SOIC Package TSSOP Package mW Tstg TL Storage Temperature - 65 to + 150 260 _C _C Lead Temperature, 1 mm from Case for 10 Seconds (Plastic DIP, SOIC or TSSOP Package) *Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. Derating -- Plastic DIP: - 10 mW/_C from 65_ to 125_C EIAJ/SOIC Package: - 7 mW/_C from 65_ to 125_C TSSOP Package: - 6.1 mW/_C from 65_ to 125_C For high frequency or heavy load considerations, see Chapter 2 of the ON Semiconductor High-Speed CMOS Data Book (DL129/D). This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, Vin and Vout should be constrained to the range GND (Vin or Vout) VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open. I/O pins must be connected to a properly terminated line or bus. v v RECOMMENDED OPERATING CONDITIONS Symbol VCC VIS Vin TA Parameter Min 2.0 Max Unit V V V V Positive DC Supply Voltage (Referenced to GND) Analog Input Voltage (Referenced to GND) Digital Input Voltage (Referenced to GND) Static or Dynamic Voltage Across Switch 12.0 GND GND -- VCC VCC 1.2 VIO* tr, tf Operating Temperature, All Package Types - 55 0 0 0 0 0 + 125 1000 600 500 400 250 _C ns Input Rise and Fall Time, ON/OFF Control Inputs (Figure 10) VCC = 2.0 V VCC = 3.0 V VCC = 4.5 V VCC = 9.0 V VCC = 12.0 V *For voltage drops across the switch greater than 1.2 V (switch on), excessive VCC current may be drawn; i.e., the current out of the switch may contain both VCC and switch input components. The reliability of the device will be unaffected unless the Maximum Ratings are exceeded. DC ELECTRICAL CHARACTERISTIC Digital Section (Voltages Referenced to GND) VCC V 2.0 3.0 4.5 9.0 12.0 2.0 3.0 4.5 9.0 12.0 Guaranteed Limit Symbol VIH Parameter Test Conditions - 55 to 25_C 1.5 2.1 3.15 6.3 8.4 0.5 0.9 1.35 2.7 3.6 v 85_C v 125_C 1.5 2.1 3.15 6.3 8.4 0.5 0.9 1.35 2.7 3.6 1.5 2.1 3.15 6.3 8.4 0.5 0.9 1.35 2.7 3.6 Unit V Minimum High-Level Voltage ON/OFF Control Inputs Ron = Per Spec VIL Maximum Low-Level Voltage ON/OFF Control Inputs Ron = Per Spec V Iin Maximum Input Leakage Current ON/OFF Control Inputs Maximum Quiescent Supply Current (per Package) Vin = VCC or GND Vin = VCC or GND VIO = 0 V 12.0 0.1 2 4 1.0 20 40 1.0 40 160 A A ICC 6.0 12.0 NOTE: Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High-Speed CMOS Data Book (DL129/D). http://onsemi.com 2 MC74HC4066A DC ELECTRICAL CHARACTERISTICS Analog Section (Voltages Referenced to GND) IIIIIIIIIIIIIIIIIIIII I II I I I I I IIIIIIIIIIIII II III I I I I I II I I I I I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I I I I I II I I I I I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I I I I I II I I II I I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I III I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I I I I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I I I I II I I I I I II I I I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I III I I I I I II I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I I I Guaranteed Limit Symbol Ron Parameter Test Conditions VCC V 2.0 3.0 4.5 9.0 12.0 - 55 to 25_C -- -- 120 70 70 -- -- 70 50 30 -- 20 15 15 v 85_C v 125_C -- -- 160 85 85 -- -- 85 60 60 -- 25 20 20 -- -- 200 100 100 -- -- 100 80 80 -- 30 25 25 Unit Maximum "ON" Resistance Vin = VIH VIS = VCC to GND IS 2.0 mA (Figures 1, 2) v v Vin = VIH VIS = VCC or GND (Endpoints) IS 2.0 mA (Figures 1, 2) 2.0 3.0 4.5 9.0 12.0 2.0 4.5 9.0 12.0 Ron Maximum Difference in "ON" Resistance Between Any Two Channels in the Same Package Vin = VIH VIS = 1/2 (VCC - GND) IS 2.0 mA v Ioff Maximum Off-Channel Leakage Current, Any One Channel Vin = VIL VIO = VCC or GND Switch Off (Figure 3) Vin = VIH VIS = VCC or GND (Figure 4) 12.0 0.1 0.5 1.0 A Ion Maximum On-Channel Leakage Current, Any One Channel 12.0 0.1 0.5 1.0 A At supply voltage (VCC) approaching 3 V the analog switch-on resistance becomes extremely non-linear. Therefore, for low-voltage operation, it is recommended that these devices only be used to control digital signals. NOTE: Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High-Speed CMOS Data Book (DL129/D). AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, ON/OFF Control Inputs: tr = tf = 6 ns) IIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I I IIIII II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I I I I II I I I II I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I I I I I II I I II II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I I I I I II I I I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I I I I II I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I III I I I I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I Guaranteed Limit Symbol tPLH, tPHL Parameter VCC V 2.0 3.0 4.5 9.0 12.0 2.0 3.0 4.5 9.0 12.0 2.0 3.0 4.5 9.0 12.0 -- -- -- - 55 to 25_C 40 30 5 5 5 80 60 20 20 20 80 45 20 20 20 10 v 85_C v 125_C 50 40 7 7 7 90 70 25 25 25 90 50 25 25 25 10 60 50 8 8 8 Unit ns Maximum Propagation Delay, Analog Input to Analog Output (Figures 8 and 9) tPLZ, tPHZ Maximum Propagation Delay, ON/OFF Control to Analog Output (Figures 10 and 11) 110 80 35 35 35 ns tPZL, tPZH Maximum Propagation Delay, ON/OFF Control to Analog Output (Figures 10 and 1 1) 100 60 30 30 30 10 ns C Maximum Capacitance ON/OFF Control Input pF Control Input = GND Analog I/O Feedthrough 35 1.0 35 1.0 35 1.0 NOTES: 1. For propagation delays with loads other than 50 pF, see Chapter 2 of the ON Semiconductor High-Speed CMOS Data Book (DL129/D). 2. Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High-Speed CMOS Data Book (DL129/D). Typical @ 25C, VCC = 5.0 V CPD Power Dissipation Capacitance (Per Switch) (Figure 13)* 15 pF * Used to determine the no-load dynamic power consumption: P D = C PD V CC 2 f + I CC V CC . For load considerations, see Chapter 2 of the ON Semiconductor High-Speed CMOS Data Book (DL129/D). http://onsemi.com 3 MC74HC4066A ADDITIONAL APPLICATION CHARACTERISTICS (Voltages Referenced to GND Unless Noted) III I I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II II I II II I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIII I II I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II III I I I II II I I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I II I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I II II I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I III I I I II I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIII I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I II I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIII II II I I I III I I I II I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I III I I I II I II I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII Symbol BW Parameter Test Conditions VCC V 4.5 9.0 12.0 4.5 9.0 12.0 4.5 9.0 12.0 4.5 9.0 12.0 4.5 9.0 12.0 4.5 9.0 12.0 4.5 9.0 12.0 Limit* 25_C 54/74HC 150 160 160 Unit Maximum On-Channel Bandwidth or Minimum Frequency Response (Figure 5) fin = 1 MHz Sine Wave Adjust fin Voltage to Obtain 0 dBm at VOS Increase fin Frequency Until dB Meter Reads - 3 dB RL = 50 , CL = 10 pF MHz -- Off-Channel Feedthrough Isolation (Figure 6) fin Sine Wave Adjust fin Voltage to Obtain 0 dBm at VIS fin = 10 kHz, RL = 600 , CL = 50 pF - 50 - 50 - 50 - 40 - 40 - 40 60 130 200 30 65 100 dB fin = 1.0 MHz, RL = 50 , CL = 10 pF -- Feedthrough Noise, Control to Switch (Figure 7) Vin 1 MHz Square Wave (tr = tf = 6 ns) Adjust RL at Setup so that IS = 0 A RL = 600 , CL = 50 pF RL = 10 k, CL = 10 pF v mVPP -- Crosstalk Between Any Two Switches (Figure 12) fin Sine Wave Adjust fin Voltage to Obtain 0 dBm at VIS fin = 10 kHz, RL = 600 , CL = 50 pF - 70 - 70 - 70 - 80 - 80 - 80 dB fin = 1.0 MHz, RL = 50 , CL = 10 pF THD Total Harmonic Distortion (Figure 14) fin = 1 kHz, RL = 10 k, CL = 50 pF THD = THDMeasured - THDSource VIS = 4.0 VPP sine wave VIS = 8.0 VPP sine wave VIS = 11.0 VPP sine wave % 4.5 9.0 12.0 0.10 0.06 0.04 *Guaranteed limits not tested. Determined by design and verified by qualification. http://onsemi.com 4 MC74HC4066A TBD TBD Figure 1a. Typical On Resistance, VCC = 2.0 V Figure 1b. Typical On Resistance, VCC = 4.5 V TBD TBD Figure 1c. Typical On Resistance, VCC = 6.0 V Figure 1d. Typical On Resistance, VCC = 9.0 V PLOTTER TBD PROGRAMMABLE POWER SUPPLY - + MINI COMPUTER DC ANALYZER VCC DEVICE UNDER TEST ANALOG IN COMMON OUT GND Figure 1e. Typical On Resistance, VCC = 12 V Figure 2. On Resistance Test Set-Up http://onsemi.com 5 MC74HC4066A VCC VCC GND VCC A OFF 14 VCC A GND ON 14 N/C VCC 7 SELECTED CONTROL INPUT VIL 7 SELECTED CONTROL INPUT VIH Figure 3. Maximum Off Channel Leakage Current, Any One Channel, Test Set-Up Figure 4. Maximum On Channel Leakage Current, Test Set-Up VCC 14 fin 0.1F ON VOS fin 0.1F VIS OFF RL SELECTED CONTROL INPUT 7 VCC 14 VOS CL* dB METER CL* dB METER 7 SELECTED CONTROL INPUT VCC *Includes all probe and jig capacitance. *Includes all probe and jig capacitance. Figure 5. Maximum On-Channel Bandwidth Test Set-Up Figure 6. Off-Channel Feedthrough Isolation, Test Set-Up VCC/2 14 RL OFF/ON VCC VCC/2 RL IS VOS CL* VCC ANALOG IN tPLH 50% ANALOG OUT 50% GND tPHL VCC GND Vin 1 MHz tr = tf = 6 ns CONTROL 7 SELECTED CONTROL INPUT *Includes all probe and jig capacitance. Figure 7. Feedthrough Noise, ON/OFF Control to Analog Out, Test Set-Up Figure 8. Propagation Delays, Analog In to Analog Out http://onsemi.com 6 MC74HC4066A VCC 14 ANALOG IN ON CL* 50% ANALOG OUT 50% *Includes all probe and jig capacitance. tPZH tPHZ 90% VOH HIGH IMPEDANCE ANALOG OUT TEST POINT CONTROL 90% 50% 10% tPZL tPLZ tr tf VCC GND HIGH IMPEDANCE 10% VOL 7 SELECTED CONTROL INPUT VCC Figure 9. Propagation Delay Test Set-Up Figure 10. Propagation Delay, ON/OFF Control to Analog Out VIS VCC RL 14 ON 0.1 F TEST POINT OFF VCC OR GND RL SELECTED CONTROL INPUT 7 VCC/2 RL CL* RL CL* fin VOS POSITION 1 WHEN TESTING tPHZ AND tPZH 1 2 VCC 1 2 ON/OFF CL* SELECTED CONTROL INPUT 7 POSITION 2 WHEN TESTING tPLZ AND tPZL VCC 14 1 k VCC/2 VCC/2 *Includes all probe and jig capacitance. *Includes all probe and jig capacitance. Figure 11. Propagation Delay Test Set-Up Figure 12. Crosstalk Between Any Two Switches, Test Set-Up VCC A 14 N/C OFF/ON N/C 0.1 F fin ON RL SELECTED CONTROL INPUT VCC/2 7 SELECTED CONTROL INPUT VCC CL* VIS VCC VOS TO DISTORTION METER 7 ON/OFF CONTROL *Includes all probe and jig capacitance. Figure 13. Power Dissipation Capacitance Test Set-Up Figure 14. Total Harmonic Distortion, Test Set-Up http://onsemi.com 7 MC74HC4066A 0 - 10 - 20 - 30 dBm - 40 - 50 - 60 - 70 - 80 - 90 1.0 2.0 FREQUENCY (kHz) 3.0 DEVICE SOURCE FUNDAMENTAL FREQUENCY Figure 15. Plot, Harmonic Distortion APPLICATION INFORMATION The ON/OFF Control pins should be at VCC or GND logic levels, VCC being recognized as logic high and GND being recognized as a logic low. Unused analog inputs/outputs may be left floating (not connected). However, it is advisable to tie unused analog inputs and outputs to VCC or GND through a low value resistor. This minimizes crosstalk and feedthrough noise that may be picked-up by the unused I/O pins. The maximum analog voltage swings are determined by the supply voltages VCC and GND. The positive peak analog voltage should not exceed VCC. Similarly, the negative peak analog voltage should not go below GND. In the example below, the difference between VCC and GND is twelve volts. Therefore, using the configuration in Figure 16, a maximum analog signal of twelve volts peak-to-peak can be controlled. When voltage transients above VCC and/or below GND are anticipated on the analog channels, external diodes (Dx) are recommended as shown in Figure 17. These diodes should be small signal, fast turn-on types able to absorb the maximum anticipated current surges during clipping. An alternate method would be to replace the Dx diodes with MOsorbs (ON Semiconductor high current surge protectors). MOsorbs are fast turn-on devices ideally suited for precise DC protection with no inherent wear out mechanism. VCC = 12 V + 12 V 0V 14 ANALOG I/O ON ANALOG O/I + 12 V 0V Dx VCC 16 ON Dx VCC SELECTED CONTROL INPUT 7 VCC Dx Dx SELECTED CONTROL INPUT 7 OTHER CONTROL INPUTS (VCC OR GND) OTHER CONTROL INPUTS (VCC OR GND) Figure 16. 12 V Application Figure 17. Transient Suppressor Application http://onsemi.com 8 MC74HC4066A +5 V +5 V ANALOG SIGNALS R* LSTTL/ NMOS R* R* R* 5 6 14 15 R* = 2 TO 10 k 14 ANALOG SIGNALS ANALOG SIGNALS HCT BUFFER 5 6 14 15 14 ANALOG SIGNALS HC4066A LSTTL/ NMOS HC4066A CONTROL INPUTS 7 CONTROL INPUTS 7 a. Using Pull-Up Resistors b. Using HCT Buffer Figure 18. LSTTL/NMOS to HCMOS Interface VDD = 5 V VCC = 5 TO 12 V 13 3 5 7 9 11 14 1 16 ANALOG SIGNALS 14 ANALOG SIGNALS HC4066A MC14504 2 4 6 8 10 5 6 14 15 CONTROL INPUTS 7 Figure 19. TTL/NMOS-to-CMOS Level Converter Analog Signal Peak-to-Peak Greater than 5 V (Also see HC4316A) CHANNEL 4 1 OF 4 SWITCHES 1 OF 4 SWITCHES COMMON I/O 1 OF 4 SWITCHES 1 OF 4 SWITCHES - INPUT 1 OF 4 SWITCHES + 0.01 F 1 2 34 CONTROL INPUTS LF356 OR EQUIVALENT OUTPUT CHANNEL 3 CHANNEL 2 CHANNEL 1 Figure 20. 4-Input Multiplexer Figure 21. Sample/Hold Amplifier http://onsemi.com 9 MC74HC4066A PACKAGE DIMENSIONS PDIP-14 N SUFFIX CASE 646-06 ISSUE L 14 8 NOTES: 1. LEADS WITHIN 0.13 (0.005) RADIUS OF TRUE POSITION AT SEATING PLANE AT MAXIMUM MATERIAL CONDITION. 2. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 3. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 4. ROUNDED CORNERS OPTIONAL. DIM A B C D F G H J K L M N INCHES MIN MAX 0.715 0.770 0.240 0.260 0.145 0.185 0.015 0.021 0.040 0.070 0.100 BSC 0.052 0.095 0.008 0.015 0.115 0.135 0.300 BSC 0_ 10_ 0.015 0.039 MILLIMETERS MIN MAX 18.16 19.56 6.10 6.60 3.69 4.69 0.38 0.53 1.02 1.78 2.54 BSC 1.32 2.41 0.20 0.38 2.92 3.43 7.62 BSC 0_ 10_ 0.39 1.01 B 1 7 A F C N H G D SEATING PLANE L J K M SOIC-14 D SUFFIX CASE 751A-03 ISSUE F -A- 14 8 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. -B- 1 7 P 7 PL 0.25 (0.010) M B M G C R X 45 F SEATING PLANE D 14 PL 0.25 (0.010) M K TB S M A S J DIM A B C D F G J K M P R MILLIMETERS MIN MAX 8.75 8.55 4.00 3.80 1.75 1.35 0.49 0.35 1.25 0.40 1.27 BSC 0.25 0.19 0.25 0.10 7 0 6.20 5.80 0.50 0.25 INCHES MIN MAX 0.337 0.344 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0 7 0.228 0.244 0.010 0.019 http://onsemi.com 10 MC74HC4066A PACKAGE DIMENSIONS TSSOP-14 DT SUFFIX CASE 948G-01 ISSUE O 14X K REF NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE -W-. DIM A B C D F G H J J1 K K1 L M MILLIMETERS MIN MAX 4.90 5.10 4.30 4.50 --- 1.20 0.05 0.15 0.50 0.75 0.65 BSC 0.50 0.60 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 BSC 0_ 8_ INCHES MIN MAX 0.193 0.200 0.169 0.177 --- 0.047 0.002 0.006 0.020 0.030 0.026 BSC 0.020 0.024 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252 BSC 0_ 8_ 0.10 (0.004) 0.15 (0.006) T U S M TU S V S N 2X L/2 14 8 0.25 (0.010) M L PIN 1 IDENT. 1 7 B -U- N F DETAIL E K K1 J J1 0.15 (0.006) T U S A -V- SECTION N-N -W- C 0.10 (0.004) -T- SEATING PLANE D G H DETAIL E SOEIAJ-14 F SUFFIX CASE 965-01 ISSUE O NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS AND ARE MEASURED AT THE PARTING LINE. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 5. THE LEAD WIDTH DIMENSION (b) DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE LEAD WIDTH DIMENSION AT MAXIMUM MATERIAL CONDITION. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT. MINIMUM SPACE BETWEEN PROTRUSIONS AND ADJACENT LEAD TO BE 0.46 ( 0.018). DIM A A1 b c D E e HE 0.50 LE M Q1 Z MILLIMETERS MIN MAX --- 2.05 0.05 0.20 0.35 0.50 0.18 0.27 9.90 10.50 5.10 5.45 1.27 BSC 7.40 8.20 0.50 0.85 1.10 1.50 10 _ 0_ 0.70 0.90 --- 1.42 INCHES MIN MAX --- 0.081 0.002 0.008 0.014 0.020 0.007 0.011 0.390 0.413 0.201 0.215 0.050 BSC 0.291 0.323 0.020 0.033 0.043 0.059 10 _ 0_ 0.028 0.035 --- 0.056 14 8 LE Q1 E HE M_ L DETAIL P 1 7 Z D e A VIEW P b 0.13 (0.005) M A1 0.10 (0.004) http://onsemi.com 11 EE CC EE CC c MC74HC4066A ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. PUBLICATION ORDERING INFORMATION NORTH AMERICA Literature Fulfillment: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303-675-2175 or 800-344-3860 Toll Free USA/Canada Fax: 303-675-2176 or 800-344-3867 Toll Free USA/Canada Email: ONlit@hibbertco.com Fax Response Line: 303-675-2167 or 800-344-3810 Toll Free USA/Canada N. American Technical Support: 800-282-9855 Toll Free USA/Canada EUROPE: LDC for ON Semiconductor - European Support German Phone: (+1) 303-308-7140 (M-F 1:00pm to 5:00pm Munich Time) Email: ONlit-german@hibbertco.com French Phone: (+1) 303-308-7141 (M-F 1:00pm to 5:00pm Toulouse Time) Email: ONlit-french@hibbertco.com English Phone: (+1) 303-308-7142 (M-F 12:00pm to 5:00pm UK Time) Email: ONlit@hibbertco.com EUROPEAN TOLL-FREE ACCESS*: 00-800-4422-3781 *Available from Germany, France, Italy, England, Ireland CENTRAL/SOUTH AMERICA: Spanish Phone: 303-308-7143 (Mon-Fri 8:00am to 5:00pm MST) Email: ONlit-spanish@hibbertco.com ASIA/PACIFIC: LDC for ON Semiconductor - Asia Support Phone: 303-675-2121 (Tue-Fri 9:00am to 1:00pm, Hong Kong Time) Toll Free from Hong Kong & Singapore: 001-800-4422-3781 Email: ONlit-asia@hibbertco.com JAPAN: ON Semiconductor, Japan Customer Focus Center 4-32-1 Nishi-Gotanda, Shinagawa-ku, Tokyo, Japan 141-8549 Phone: 81-3-5740-2745 Email: r14525@onsemi.com ON Semiconductor Website: http://onsemi.com For additional information, please contact your local Sales Representative. http://onsemi.com 12 MC74HC4066A/D |
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